Chip Multi Processors (CMPs) such as Intel® Corporation's 48-core Single Chip Computer SCC, and cluster-based single-platform architectures such as Intel's micro-server, are increasingly becoming the mainstream hardware architectures for a wide range of computing platforms. In such emerging systems, the interconnect fabric consumes an ever increasing power in the quest for higher bandwidth and larger number of cores (or correspondingly nodes). Unfortunately, such interconnects do not come at a low power cost. Recent studies show that Intel's Nehalem Dual-Lane QPI, Intel's 80-core chip, and MIT's RAW chip interconnect consumes 20%, 30%, and 40%, respectively, of their uncore power. Furthermore, as technology and operating voltages continue to scale down as evidenced by Intel's 22 nm transistor technology, and near-threshold voltage proposals, the proportion of static power relative to total power is becoming increasingly more significant.
With an increasing number of core/nodes in the system, more core/nodes would be eligible to go to low power states (Intel's core/node parking model) depending on the system load. However, even though a core/node is in a low power state and not generating any interconnect traffic, its attached router remains always active in order to maintain the capability of forwarding packets on behalf of other nodes, even though it may not be necessary, resulting in relatively high interconnect power consumption with low utilization.